1. Field of the Invention
This invention relates to a control apparatus for a power converter, each phase of the power converter may output three levels of voltages, and more specifically to a control apparatus that may minimize a switching loss of a semiconductor switching device at a time of switching by minimizing the number of turning ON/OFF (switching) of the semiconductor switching device and may control a waveform of output voltage suitably.
2. Description of the Background
FIG. 1 is a circuit diagram showing a main circuit of a power converter that may output three levels of voltages and a conventional control apparatus for the power converter.
In FIG. 1, a converter 1 includes two DC (Direct Current) capacitors 2 and 3, twelve semiconductor switching devices S11, S12, S13, S14, S21, S22, S23, S24, S31, S32, S33 and S34, and diodes. A DC power source 4 is connected to the converter 1. A controller for the converter 1 includes a command voltage generator 5, a carrier wave generator 6, six comparators 7, 8, 9, 10, 11 and 12, and six inverters 13, 14, 15, 16, 17 and 18. G11-G14, G21-G24 and G31-G34 represent gate signals for the semiconductor switching devices S11-S14, S21-S24 and S31-S34 respectively.
FIG. 2 is one example of a waveform that indicates an operation of the controller for the converter 1 in FIG. 1. The operation of each portion of the controller is described referring to FIG. 2.
The command voltage generator 5 generates output voltage commands VU*, VV* and VW* to be output from the converter 1 on the basis of a power or a current flowing in a load connected to AC (Alternating Current) terminals of the converter 1. The carrier wave generator 6 generates two carrier waves VCP and VCN in order to modulate the output voltage commands VU*, VV* and VW*. The carrier wave VCP has the same triangular waveform as the carrier wave VCN. The carrier wave VCP sets the minimum value at 0 (zero), while the carrier wave VCN sets the maximum value at 0 (zero) . The comparator 7 compares the output voltage command VU* with the carrier wave VCP, and outputs "1" as the gate signal G11 of the semiconductor switching device S11 and "0" as the gate signal G13 of the semiconductor switching device S13 at the time that the output voltage command VU* is higher than the carrier wave VCP. On the contrary, where the output voltage command VU* is lower than the carrier wave VCP, the gate signal G11 is made "0" and the gate signal G13 is made "1". A gate signal "1" represents a command for turning on the corresponding semiconductor switching device, while a gate signal "0" represents a command for turning off the corresponding semiconductor switching device. The inverter 13 inverts a logic of the gate signal G11 and G13.
Likewise, the comparator 8 and the inverter 14 determine the gate signals G12 and G14 of the semiconductor switching devices S12 and S14 on the basis of the output voltage commands VU* and the carrier wave VCN.
Description of the operation of the other comparators and inverters in FIG. 1 are omitted, because the other comparators and inverters operate in the same way as the comparators 7 and 8, and the inverters 13 and 14.
The corresponding semiconductor switching devices S11-S34 turn on and off in response to the above determined gate signals G11-G34, thereby converting a DC voltage supplied from the DC power source 4 into output voltages based on the output voltage commands VU*, VV* and VW*. The DC capacitors 2 and 3 are used for smoothing and stabilizing an electric power supplied from the DC power source 4.
As described above, the semiconductor switching devices S11-S34 repeatedly turn on and off at a frequency based on the frequency of the carrier waves VCP and VCN, when the converter 1 generates a suitable voltage. As switching frequency of the semiconductor switching device rises, a switching loss caused by turning on and off the semiconductor switching device increases. As a result, power efficiency of the converter 1 lowers and a converting rate of voltage, that is called "utilization factor", is also reduced due to an increase of unnecessary switching.
Imbalance of switching losses among the semiconductor switching devices S11-S34 may occur depending on conditions of an output voltage or an output current of the converter 1, thereby raising a temperature of the only one part of the semiconductor switching devices due to heat loss, and giving rise to a thermal stress. With the advance of the thermal stress, the semiconductor switching devices may break.
In case that a current flows into the DC capacitor through the only semiconductor switching devices S12, S22, S32, S13, S23 and S33 and diodes which are directly connected to the AC terminals of the converter 1, that is, at least one phase of the converter 1 has the same potential as a joint of the DC capacitors 2 and 3 has, directions of currents flowing into the DC capacitors 2 and 3 are different from each other, whereby voltage imbalance between the DC capacitors 2 and 3 may occur. With the advance of the voltage imbalance, an output voltage of the converter 1 may not be controlled suitably, or the main circuit may break because of the excessive increase of voltages of either DC capacitor 2 or 3.